1. Field of the Invention
The present invention relates to a slew rate control device using a switching capacitor, and more particularly, to a slew rate control device using a switching capacitor with which it is possible to control rising and falling slew rates by turning on and off a signal in an amplitude shift keying process.
2. Description of the Related Art
In general, a slew rate means the amount of change in rising and falling of an output per unit time with respect to a step change of a control input signal. The slew rate has a characteristic that sensitively responds to influence of an external environment or a temperature.
FIG. 1 is a circuit diagram of a voltage controlled oscillator according to the related art. In FIG. 1, a CK terminal 10 is a portion to which a digital pulse signal (hereinafter, referred to as a clock signal) for controlling an operation of a voltage controlled oscillator (VCO) 20 is input. The voltage controlled oscillator 20 performs modulation in an amplitude shift keying manner in response to an input of the digital pulse signal. That is, when a high signal is input to the CK terminal 10, the voltage controlled oscillator 20 is operated, and when a low signal is input to the CK terminal 10, the voltage controlled oscillator 20 is not operated.
FIG. 2 is a diagram for describing an amplitude shift keying process of FIG. 1. (a) of FIG. 2 illustrates a general output waveform of the voltage controlled oscillator 20. (b) of FIG. 2 illustrates a waveform of the clock signal used to control driving of the voltage controlled oscillator 20.
(c) of FIG. 2 illustrates an output waveform of the voltage controlled oscillator 20 when the clock signal is applied, and it can be seen that the voltage controlled oscillator 20 is turned on or off depending on high and low states of the input clock signal. Here, a signal waveform of FIG. 2 corresponds to an ideal interpretation where a slew rate is not generated.
FIG. 3 illustrates a waveform in which the slew rate is generated when the circuit of FIG. 1 is driven. Unlike an ideal amplitude shift keying result of (c) of FIG. 2, it can be seen from FIG. 3 that a rising slope Sr or a falling slope Sf is generated at the time when the clock signal is changed to a high state or a low state.
The slew rate is generated by a parasitic capacitor presented on the circuit of FIG. 1. Further, when the rising slope and the falling slope are not identical, quality of the signal may be degraded. In the related art, in order to solve an unbalance problem of the slew rate, an additional control circuit that controls the slew rate is needed, so that the circuit may be complicated due to the additional control circuit.
The background technology of the present invention is disclosed in Korean Patent Publication No. 2001-0073701 (published on Aug. 1, 2001).